What is the concept of 2 nano chip?The diameter of a hair filament is typically 50000 nanometers, and 2 nanometers is equivalent to cutting 25000 parts of the hair filament axially.
Previously, after announcing the successful development of a 2 nm chip, IBM announced that a 2 nm chip the size of a nail could hold up to 50 billion transistors. Atmel
For consumers, new technologies can reduce chip energy consumption by 75% and improve phone performance, such as extending battery life by nearly four times.
However, after reaching the 2 nm process, involving the updating of the original process architecture, materials, and equipment, and technological innovation, it means that the industrial structure may be reshuffled, which is one of the reasons why many enterprises, even countries and regions have decided to bet on 2 nm.
In the process of chip manufacturing, it can be divided into a main industrial chain and a supporting industrial chain: the main industrial chain includes chip design, manufacturing, and packaging; The supporting industrial chain includes IP, EDA, equipment, materials, etc.
The high cost mainly consists of Broadcom labor and research and development expenses, streaming expenses, IP and EDA tool licensing fees, and other components. At the same time, the investment in the wafer factory, wafer manufacturing, and related equipment costs involved in the chip manufacturing process will also be allocated to the overall cost of the chip.
Therefore, with the evolution of the process, the research and development costs of semiconductor chips have also soared.According to a recent analysis meeting by Marvell executives, during the 28nm process, the cost of designing a chip was only $42.8 million. During the 22nm and 16nm processes, the chip design cost has steadily increased, but the range is still controllable, with the design cost of 16nm chips being $89.8 million.
However, below 10 nm, chip design costs have started to skyrocket simultaneously. Marvell executives further pointed out that the cost of chip design at 7nm has reached $249 million, the cost of chip design at 5nm has risen to $449 million, the cost of chip design at 3nm has reached as high as $581 million, and the cost of chip design at 2nm has further soared to $725 million.
Currently, driven by "Moore's Law", the scale of integrated circuit design and manufacturing processes are becoming increasingly complex. Designers must rely on NXP Semiconductors EDA tools to complete circuit design, layout design, layout verification, performance analysis, and other work. Therefore, the proportion of software in chip costs increases as chip manufacturing continues to improve.
According to the display, at 28 nm, software accounted for the largest cost in the chip design process, but this situation was reversed at 22 nm and 16 nm, with software accounting for only a small portion of the cost in chip design. After entering 10 nm, this situation has reappeared, and software has once again become a significant part of chip design costs.
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